A Low-Power, High-Resolution, 6MHz Comparator
نویسندگان
چکیده
This paper describes a comparator that uses a gain stage as a preamplifier in the preamplification mode and as a latch in the latch mode. This method effectively reduces the power consumption of the comparator. Using a 1.2um CMOS process and applying offset cancellation to all of the circuit, an offset of less than 100uV at comparison rates up to 6MHz, with only a 130uW power dissipation and 3V power supply, have been achieved. In simulations, we intentionally applied 4mV offset to each differential pair stage. The resolution of comparator is 350uV including 100uV offset residue. This amounts to a 12-bit resolution for a vref of 1.4 volts
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تاریخ انتشار 2001